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CHERIoT RTOS
A compartmentalised RTOS for CHERIoT hardware
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A simple driver for the Sonata's GPIO. More...
#include <platform-gpio.hh>


Public Types | |
| enum | : uint32_t { PcIntStatus = 1U << 31 } |
| Control Register Fields. More... | |
| enum | PcIntMode : uint32_t { AnyEdge = 0 , RisingEdge = 1 , FallingEdge = 2 , LowLevel = 3 } |
| enum | : uint32_t { PcIntModeSelect = PcIntModeBits << 0 , PcIntInputSelect = 1U << 3 , PcIntEnable = 1U << 31 } |
| Status Register Fields. More... | |
Public Member Functions | |
| void | set_output (uint32_t index, bool value) volatile |
| Set the output bit for a given GPIO pin index to a specified value. | |
| void | set_output_enable (uint32_t index, bool enable) volatile |
| Set the output enable bit for a given GPIO pin index. | |
| void | enable_interrupts (bool enable) volatile |
| Enable GPIO pin-change interrupts for this instance. | |
| void | clear_interrupt_mask () volatile |
| Clear the GPIO pin-change interrupt mask. | |
| void | set_interrupt (uint32_t index, bool enable) volatile |
| Only GPIO pins explicitly enabled can trigger an interrupt. | |
| void | debounce_interrupt (bool debounce) volatile |
| Whether to use the raw or debounced input for the GPIO pin-change interrupt. | |
| void | change_interrupt_mode (enum PcIntMode mode) volatile |
| Select the pin-change interrupt mode. | |
| void | clear_interrupt_status () volatile |
| bool | read_input (uint32_t index) volatile |
| Read the input value for a given GPIO pin index. | |
| bool | read_debounced_input (uint32_t index) volatile |
| Read the debounced input value for a given GPIO pin index. | |
| bool | read_interrupt_status () volatile |
Static Public Member Functions | |
| static constexpr uint32_t | gpio_bit (uint32_t index, uint32_t mask) |
| Returns a mask with a single bit set corresponding to the given GPIO index or 0 if that bit is not set in mask. | |
Public Attributes | |
| uint32_t | output |
| uint32_t | input |
| uint32_t | debouncedInput |
| uint32_t | outputEnable |
| uint32_t | control |
| uint32_t | status |
| uint32_t | pcintMask |
Static Public Attributes | |
| static constexpr uint32_t | PcIntModeBits = 2 |
A simple driver for the Sonata's GPIO.
This struct represents a single GPIO instance, and the methods available to interact with that GPIO. This class should usually be used via one the aliases / subclasses defined below which are specialised to the GPIO instance. e.g. see SonataGpioBoard.
Documentation source can be found at: https://github.com/lowRISC/sonata-system/blob/9f794fe3bd4eec8d1a01ee81da97a7f2cec0b452/doc/ip/gpio.md
Rendered documentation is served from: https://lowrisc.org/sonata-system/doc/ip/gpio.html
| OutputMask | The mask of bits of the output register that contain meaningful GPIO output. |
| InputMask | The mask of bits of the input and debouncedInput registers that contain meaningful GPIO input. This is usually the same as OutputMask if the instance has the same number of input and output pins. |
| OutputEnableMask | The mask of bits for the output_enable register, again this is usually the same as OutputMask. |
| PcIntMask | The mask of bits for the pcint_mask register, this is the same as the InputMask. |
Definition at line 40 of file platform-gpio.hh.
| anonymous enum : uint32_t |
Control Register Fields.
| Enumerator | |
|---|---|
| PcIntStatus | Pin-change interrupt status. Write 1 to clear. |
Definition at line 51 of file platform-gpio.hh.
| anonymous enum : uint32_t |
Status Register Fields.
Definition at line 68 of file platform-gpio.hh.
| enum SonataGpioBase::PcIntMode : uint32_t |
Definition at line 58 of file platform-gpio.hh.
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inline |
Select the pin-change interrupt mode.
Definition at line 185 of file platform-gpio.hh.
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inline |
Clear the GPIO pin-change interrupt mask.
Definition at line 143 of file platform-gpio.hh.
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inline |
Definition at line 190 of file platform-gpio.hh.
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inline |
Whether to use the raw or debounced input for the GPIO pin-change interrupt.
Definition at line 170 of file platform-gpio.hh.
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inline |
Enable GPIO pin-change interrupts for this instance.
Definition at line 128 of file platform-gpio.hh.
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inlinestaticconstexpr |
Returns a mask with a single bit set corresponding to the given GPIO index or 0 if that bit is not set in mask.
Definition at line 83 of file platform-gpio.hh.
Referenced by SonataGpioBase< 0x0000 '3FFF >::read_debounced_input(), SonataGpioBase< 0x0000 '3FFF >::read_input(), SonataGpioBase< 0x0000 '3FFF >::set_interrupt(), SonataGpioBase< 0x0000 '3FFF >::set_output(), and SonataGpioBase< 0x0000 '3FFF >::set_output_enable().
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inline |
Read the debounced input value for a given GPIO pin index.
For this to be meaningful, the corresponding pin must be configured to be an input first (set output enable to false for the given index). If given an invalid GPIO pin (outside the input mask), then this value will always be false.
Definition at line 214 of file platform-gpio.hh.
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inline |
Read the input value for a given GPIO pin index.
For this to be meaningful, the corresponding pin must be configured to be an input first (set output enable to false for the given index). If given an invalid GPIO pin (outside the input mask), then this value will always be false.
Definition at line 202 of file platform-gpio.hh.
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inline |
Definition at line 219 of file platform-gpio.hh.
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inline |
Only GPIO pins explicitly enabled can trigger an interrupt.
Enabling a GPIO pin for interrupts will set the corresponding bit in the pin-change interrupt mask.
Definition at line 153 of file platform-gpio.hh.
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inline |
Set the output bit for a given GPIO pin index to a specified value.
This will only have an effect if the corresponding bit is first set to 1 (i.e. output) in the output_enable register, and if the pin is a valid output pin.
Definition at line 94 of file platform-gpio.hh.
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inline |
Set the output enable bit for a given GPIO pin index.
If enable is true, the GPIO pin is set to output. If false, it is instead set to input mode.
Definition at line 112 of file platform-gpio.hh.
| uint32_t SonataGpioBase< OutputMask, InputMask, OutputEnableMask, PcIntMask >::control |
Definition at line 46 of file platform-gpio.hh.
| uint32_t SonataGpioBase< OutputMask, InputMask, OutputEnableMask, PcIntMask >::debouncedInput |
Definition at line 44 of file platform-gpio.hh.
| uint32_t SonataGpioBase< OutputMask, InputMask, OutputEnableMask, PcIntMask >::input |
Definition at line 43 of file platform-gpio.hh.
| uint32_t SonataGpioBase< OutputMask, InputMask, OutputEnableMask, PcIntMask >::output |
Definition at line 42 of file platform-gpio.hh.
| uint32_t SonataGpioBase< OutputMask, InputMask, OutputEnableMask, PcIntMask >::outputEnable |
Definition at line 45 of file platform-gpio.hh.
| uint32_t SonataGpioBase< OutputMask, InputMask, OutputEnableMask, PcIntMask >::pcintMask |
Definition at line 48 of file platform-gpio.hh.
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staticconstexpr |
Definition at line 66 of file platform-gpio.hh.
| uint32_t SonataGpioBase< OutputMask, InputMask, OutputEnableMask, PcIntMask >::status |
Definition at line 47 of file platform-gpio.hh.