CHERIoT RTOS
A compartmentalised RTOS for CHERIoT hardware
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platform-switcher_cpu_features.hh
1// Copyright SCI Semiconductor and CHERIoT Contributors.
2// SPDX-License-Identifier: MIT
3
4#pragma once
5
6#include "ibex-csr.h"
7
8/**
9 * Flag to pass to switcher_invocation_cpu_features_set to enable or disable the
10 * Ibex I$.
11 */
12#define SWITCHER_CPU_FEATURE_CACHE_INSTRUCTION_ENABLED \
13 IbexCSR_Cpuctrlsts_IcacheEnable
14
15/**
16 * Flag to pass to switcher_invocation_cpu_features_set to enable or disable
17 * Ibex's "data independent timing" behaviors.
18 */
19#define SWITCHER_CPU_FEATURE_PLATFORM_DATA_INDEPENDENT_TIMING \
20 IbexCSR_Cpuctrlsts_DataIndependentTiming
21
22/// Default to I$ on (if supported) and "data independent timing" off.
23#define SWITCHER_CPU_FEATURE_DEFAULT IbexCSR_Cpuctrlsts_IcacheEnable
Ibex defines some custom M-mode CSRs to control some of its extensions: