Ibex defines some custom M-mode CSRs to control some of its extensions: More...

Macros
#define	IbexCSR_Cpuctrlsts_index 0x7C0U
	Index of the cpuctrlsts CSR.
#define	IbexCSR_Cpuctrlsts_IcacheEnable 0x001U
	Instruction cache enable, active high.
#define	IbexCSR_Cpuctrlsts_IcacheEnable_shift 0
#define	IbexCSR_Cpuctrlsts_DataIndependentTiming 0x002U
	Data independent timing features enabled, active high.
#define	IbexCSR_Cpuctrlsts_DataIndependentTiming_shift 1
#define	IbexCSR_Cpuctrlsts_DummyInstructionInsertion 0x004U
	Dummy instruction insertion enabled, active high.
#define	IbexCSR_Cpuctrlsts_DummyInstructionInsertion_shift 2
#define	IbexCSR_Cpuctrlsts_DummyInstructionRate 0x038U
	Dummy instruction insertion rate.
#define	IbexCSR_Cpuctrlsts_DummyInstructionRate_shift 3
#define	IbexCSR_Cpuctrlsts_SynchronousExceptionSeen 0x040U
	Synchronous exception taken and core has not yet executed mret.
#define	IbexCSR_Cpuctrlsts_SynchronousExceptionSeen_shift 6
#define	IbexCSR_Cpuctrlsts_DoubleFaultSeen 0x080U
	Synchronous exception taken while SYNC_EXC_SEEN was asserted.
#define	IbexCSR_Cpuctrlsts_DoubleFaultSeen_shift 7
#define	IbexCSR_Cpuctrlsts_IcacheScrambleKeyValid 0x100U
	Instruction cache scrambling key is valid.
#define	IbexCSR_Cpuctrlsts_IcacheScrambleKeyValid_shift 8
#define	IbexCSR_Secureseed_index 0x7C1U
	Index of the secureseed CSR.

Detailed Description

Ibex defines some custom M-mode CSRs to control some of its extensions:

cpuctrlsts: "CPU Control and Status Register"
secureseed: "Security Feature Seed Register"

See https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html

The convention for these names is that they begin with IbexCSR_ followed by the upstream name of the CSR. _index then gives that CSR's index. Each field within has two preprocessor macros associated: one, named by the field without suffix, provides a numeric value with a span of asserted bits covering all associated bits within the 32-bit CSR word, and the other, named with a _shift suffix, gives the 0-based bit index of the least significant bit of the field's span.

Definition in file ibex-csr.h.

Macro Definition Documentation

◆ IbexCSR_Cpuctrlsts_DataIndependentTiming

#define IbexCSR_Cpuctrlsts_DataIndependentTiming 0x002U

Data independent timing features enabled, active high.

Definition at line 46 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_DataIndependentTiming_shift

#define IbexCSR_Cpuctrlsts_DataIndependentTiming_shift 1

Definition at line 47 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_DoubleFaultSeen

#define IbexCSR_Cpuctrlsts_DoubleFaultSeen 0x080U

Synchronous exception taken while SYNC_EXC_SEEN was asserted.

Definition at line 72 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_DoubleFaultSeen_shift

#define IbexCSR_Cpuctrlsts_DoubleFaultSeen_shift 7

Definition at line 73 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_DummyInstructionInsertion

#define IbexCSR_Cpuctrlsts_DummyInstructionInsertion 0x004U

Dummy instruction insertion enabled, active high.

See https://ibex-core.readthedocs.io/en/latest/03_reference/security.html#security

Definition at line 55 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_DummyInstructionInsertion_shift

#define IbexCSR_Cpuctrlsts_DummyInstructionInsertion_shift 2

Definition at line 56 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_DummyInstructionRate

#define IbexCSR_Cpuctrlsts_DummyInstructionRate 0x038U

Dummy instruction insertion rate.

See https://ibex-core.readthedocs.io/en/latest/03_reference/security.html#security

Definition at line 64 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_DummyInstructionRate_shift

#define IbexCSR_Cpuctrlsts_DummyInstructionRate_shift 3

Definition at line 65 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_IcacheEnable

#define IbexCSR_Cpuctrlsts_IcacheEnable 0x001U

Instruction cache enable, active high.

Definition at line 42 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_IcacheEnable_shift

#define IbexCSR_Cpuctrlsts_IcacheEnable_shift 0

Definition at line 43 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_IcacheScrambleKeyValid

#define IbexCSR_Cpuctrlsts_IcacheScrambleKeyValid 0x100U

Instruction cache scrambling key is valid.

Definition at line 76 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_IcacheScrambleKeyValid_shift

#define IbexCSR_Cpuctrlsts_IcacheScrambleKeyValid_shift 8

Definition at line 77 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_index

#define IbexCSR_Cpuctrlsts_index 0x7C0U

Index of the cpuctrlsts CSR.

See https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#cpu-control-and-status-register-cpuctrlsts

Definition at line 39 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_SynchronousExceptionSeen

#define IbexCSR_Cpuctrlsts_SynchronousExceptionSeen 0x040U

Synchronous exception taken and core has not yet executed mret.

Definition at line 68 of file ibex-csr.h.

◆ IbexCSR_Cpuctrlsts_SynchronousExceptionSeen_shift

#define IbexCSR_Cpuctrlsts_SynchronousExceptionSeen_shift 6

Definition at line 69 of file ibex-csr.h.

◆ IbexCSR_Secureseed_index

#define IbexCSR_Secureseed_index 0x7C1U

Index of the secureseed CSR.

See https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#cpu-control-and-status-register-secureseed

This CSR holds a single, 32-bit, numeric value.

Definition at line 87 of file ibex-csr.h.

Macros