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CHERIoT RTOS
A compartmentalised RTOS for CHERIoT hardware
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Generic 16550A memory-mapped register layout. More...
#include <platform-uart.hh>
Public Member Functions | |
| bool | can_write () volatile |
| Returns true if the transmit buffer is empty. | |
| bool | can_read () volatile |
| Returns true if the receive buffer is not. | |
| uint8_t | blocking_read () volatile |
| Read one byte, blocking until a byte is available. | |
| void | blocking_write (uint8_t byte) volatile |
| Write one byte, blocking until the byte is written. | |
| template<typename T = decltype(no_custom_init)> | |
| void | init (int divisor=1, T &&otherSetup=no_custom_init) volatile |
| Initialise the UART. | |
Public Attributes | |
| RegisterType | data |
| The interface to the read/write FIFOs for this UART. | |
| RegisterType | intrEnable |
| Interrupt-enabled control / status. | |
| RegisterType | intrIDandFifo |
| Interrupt identification and FIFO enable/disable. | |
| RegisterType | lineControl |
| Specifies properties of the line (stop bit, parity, and so on). | |
| RegisterType | modemControl |
| Modem control. | |
| const RegisterType | LineStatus |
| The line status word. | |
| const RegisterType | ModemStatus |
| Modem status. | |
| RegisterType | scratch |
| Scratch register. | |
Generic 16550A memory-mapped register layout.
The registers are 8 bits wide, but typically the bus supports only 4-byte (or larger) transactions and so they are padded to a 32-bit word. The template parameter allows this to be controlled.
Definition at line 17 of file platform-uart.hh.
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inline |
Read one byte, blocking until a byte is available.
Definition at line 99 of file platform-uart.hh.
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Write one byte, blocking until the byte is written.
Definition at line 110 of file platform-uart.hh.
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inline |
Returns true if the receive buffer is not.
Definition at line 91 of file platform-uart.hh.
Referenced by Uart16550< uint32_t >::blocking_read().
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Returns true if the transmit buffer is empty.
Definition at line 77 of file platform-uart.hh.
Referenced by Uart16550< uint32_t >::blocking_write().
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inline |
Initialise the UART.
Definition at line 122 of file platform-uart.hh.
Referenced by SynopsisExtended16550< DefaultBaudRate >::init().
| RegisterType Uart16550< RegisterType >::data |
The interface to the read/write FIFOs for this UART.
This is also the low byte of the divisor when the divisor latch (bit 7 of the lineControl) is set.
Definition at line 28 of file platform-uart.hh.
| RegisterType Uart16550< RegisterType >::intrEnable |
Interrupt-enabled control / status.
Write 1 to enabled, 0 to disable, to each of the low four bits:
0: Data-receive interrupt 1: Transmit holding register empty interrupt 2: Receive line status interrupts 3: Modem status interrupts.
When bit 7 of lineControl is set, this is instead the divisor-latch-high register and stores the high 8 bits of the divisor.
Definition at line 41 of file platform-uart.hh.
| RegisterType Uart16550< RegisterType >::intrIDandFifo |
Interrupt identification and FIFO enable/disable.
We only care about the low bit here, which enables the FIFO.
Definition at line 47 of file platform-uart.hh.
| RegisterType Uart16550< RegisterType >::lineControl |
Specifies properties of the line (stop bit, parity, and so on).
The only bit that we use is bit 7, the divisor latch, which enables writing the speed.
Definition at line 53 of file platform-uart.hh.
| const RegisterType Uart16550< RegisterType >::LineStatus |
The line status word.
The bits that we care about are:
0: Receive ready 5: Transmit buffer empty
Definition at line 64 of file platform-uart.hh.
| RegisterType Uart16550< RegisterType >::modemControl |
Modem control.
Definition at line 57 of file platform-uart.hh.
| const RegisterType Uart16550< RegisterType >::ModemStatus |
Modem status.
Definition at line 68 of file platform-uart.hh.
| RegisterType Uart16550< RegisterType >::scratch |