A Simple Driver for the Sonata's SPI. More...

#include <platform-spi.hh>

Public Types
enum	Interrupt : uint32_t { InterruptComplete = 1 << 4 , InterruptTransmitWatermark = 1 << 3 , InterruptTransmitEmpty = 1 << 2 , InterruptReceiveWatermark = 1 << 1 , InterruptReceiveFull = 1 << 0 }
	Sonata SPI Interrupts. More...
enum	: uint32_t { ConfigurationHalfClockPeriodMask = 0xffu << 0 , ConfigurationMSBFirst = 1u << 29 , ConfigurationClockPhase = 1u << 30 , ConfigurationClockPolarity = 1u << 31 }
	Configuration Register Fields. More...
enum	: uint32_t { ControlTransmitClear = 1 << 0 , ControlReceiveClear = 1 << 1 , ControlTransmitEnable = 1 << 2 , ControlReceiveEnable = 1 << 3 , ControlTransmitWatermarkMask = 0xf << 4 , ControlReceiveWatermarkMask = 0xf << 8 , ControlInternalLoopback = 1 << 30 , ControlSoftwareReset = 1u << 31 }
	Control Register Fields. More...
enum	: uint32_t { StatusTxFifoLevel = 0xffu << 0 , StatusRxFifoLevel = 0xffu << 8 , StatusTxFifoFull = 1u << 16 , StatusRxFifoEmpty = 1u << 17 , StatusIdle = 1u << 18 }
	Status Register Fields. More...
enum	: uint32_t { StartByteCountMask = 0x7ffu }
	Start Register Fields. More...
enum	: uint32_t { InfoTxFifoDepth = 0xffu << 0 , InfoRxFifoDepth = 0xffu << 8 }
	Info Register Fields. More...
enum	: uint32_t { ConfigurationHalfClockPeriodMask = 0xffu << 0 , ConfigurationMSBFirst = 1u << 29 , ConfigurationClockPhase = 1u << 30 , ConfigurationClockPolarity = 1u << 31 }
	Configuration Register Fields. More...
enum	: uint32_t { ControlTransmitClear = 1 << 0 , ControlReceiveClear = 1 << 1 , ControlTransmitEnable = 1 << 2 , ControlReceiveEnable = 1 << 3 , ControlTransmitWatermarkMask = 0xf << 4 , ControlReceiveWatermarkMask = 0xf << 8 }
	Control Register Fields. More...
enum	: uint32_t { StatusTxFifoLevel = 0xffu << 0 , StatusRxFifoLevel = 0xffu << 8 , StatusTxFifoFull = 1u << 16 , StatusRxFifoEmpty = 1u << 17 , StatusIdle = 1u << 18 }
	Status Register Fields. More...
enum	: uint32_t { StartByteCountMask = 0x7ffu }
	Start Register Fields. More...
using	Debug = ConditionalDebug<DebugSonataSpi, "Sonata SPI">
	Helper for conditional debug logs and assertions.

Public Member Functions
void	init (const bool ClockPolarity, const bool ClockPhase, const bool MsbFirst, const uint16_t HalfClockPeriod) volatile
	Initialises the SPI block.
void	wait_idle () volatile
	Waits for the SPI device to become idle.
void	blocking_write (const uint8_t data[], uint16_t len) volatile
	Sends len bytes from the given data buffer, where len is at most 0x7ff.
void	blocking_read (uint8_t data[], uint16_t len) volatile

Public Attributes
uint32_t	interruptState
	The Sonata SPI block doesn't currently have support for interrupts.
uint32_t	interruptEnable
uint32_t	interruptTest
uint32_t	configuration
	Configuration register.
uint32_t	control
	Controls the operation of the SPI block.
uint32_t	status
	Status information about the SPI block.
uint32_t	start
	Writes to this begin an SPI operation.
uint32_t	receiveFifo
	Data from the receive FIFO.
uint32_t	transmitFifo
	Bytes written here are pushed to the transmit FIFO.

Static Public Attributes
static constexpr bool	DebugSonataSpi = false
	Flag set when we're debugging this driver.

Detailed Description

A Simple Driver for the Sonata's SPI.

Documentation source can be found at: https://github.com/lowRISC/sonata-system/blob/1a59633d2515d4fe186a07d53e49ff95c18d9bbf/doc/ip/spi.md

Rendered documentation is served from: https://lowrisc.org/sonata-system/doc/ip/spi.html

Definition at line 15 of file platform-spi.hh.

Member Typedef Documentation

◆ Debug

using SonataSpi::Debug = ConditionalDebug<DebugSonataSpi, "Sonata SPI">

Helper for conditional debug logs and assertions.

Definition at line 147 of file platform-spi.hh.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum : uint32_t

Control Register Fields.

Enumerator
ControlTransmitClear	Write 1 to clear the transmit FIFO.
ControlReceiveClear	Write 1 to clear the receive FIFO.
ControlTransmitEnable	When set bytes from the transmit FIFO are sent. When clear the state of the outgoing spi_cipo is undefined whilst the SPI clock is running.
ControlReceiveEnable	When set incoming bits are written to the receive FIFO. When clear incoming bits are ignored.
ControlTransmitWatermarkMask	The watermark level for the transmit FIFO, depending on the value the interrupt will trigger at different points.
ControlReceiveWatermarkMask	The watermark level for the receive FIFO, depending on the value the interrupt will trigger at different points.

Definition at line 86 of file platform-spi.hh.

◆ anonymous enum

anonymous enum : uint32_t

Info Register Fields.

Enumerator
InfoTxFifoDepth	Maximum number of items in the transmit FIFO.
InfoRxFifoDepth	Maximum number of items in the receive FIFO.

Definition at line 129 of file platform-spi.hh.

◆ anonymous enum

anonymous enum : uint32_t

Control Register Fields.

Enumerator
ControlTransmitClear	Write 1 to clear the transmit FIFO.
ControlReceiveClear	Write 1 to clear the receive FIFO.
ControlTransmitEnable	When set bytes from the transmit FIFO are sent. When clear the state of the outgoing spi_cipo is undefined whilst the SPI clock is running.
ControlReceiveEnable	When set incoming bits are written to the receive FIFO. When clear incoming bits are ignored.
ControlTransmitWatermarkMask	The watermark level for the transmit FIFO, depending on the value the interrupt will trigger at different points.
ControlReceiveWatermarkMask	The watermark level for the receive FIFO, depending on the value the interrupt will trigger at different points.
ControlInternalLoopback	Internal loopback function enabled when set to 1.
ControlSoftwareReset	Software reset performed when written as 1.

Definition at line 63 of file platform-spi.hh.

◆ anonymous enum

anonymous enum : uint32_t

Status Register Fields.

Enumerator
StatusTxFifoLevel	Number of items in the transmit FIFO.
StatusRxFifoLevel	Number of items in the receive FIFO.
StatusTxFifoFull	When set the transmit FIFO is full and any data written to it will be ignored.
StatusRxFifoEmpty	When set the receive FIFO is empty and any data read from it will be undefined.
StatusIdle	When set the SPI block is idle and can accept a new start command.

Definition at line 101 of file platform-spi.hh.

◆ anonymous enum

anonymous enum : uint32_t

Start Register Fields.

Enumerator
StartByteCountMask	Number of bytes to receive/transmit in the SPI operation.

Definition at line 122 of file platform-spi.hh.

◆ anonymous enum

anonymous enum : uint32_t

Start Register Fields.

Enumerator
StartByteCountMask	Number of bytes to receive/transmit in the SPI operation.

Definition at line 137 of file platform-spi.hh.

◆ anonymous enum

anonymous enum : uint32_t

Configuration Register Fields.

Enumerator

ConfigurationHalfClockPeriodMask

The length of a half period (i.e.

positive edge to negative edge) of the SPI clock, measured in system clock cycles reduced by 1. For example, at a 50 MHz system clock, a value of 0 gives a 25 MHz SPI clock, a value of 1 gives a 12.5 MHz SPI clock, a value of 2 gives a 8.33 MHz SPI clock and so on.

Definition at line 31 of file platform-spi.hh.

◆ anonymous enum

anonymous enum : uint32_t

Status Register Fields.

Enumerator
StatusTxFifoLevel	Number of items in the transmit FIFO.
StatusRxFifoLevel	Number of items in the receive FIFO.
StatusTxFifoFull	When set the transmit FIFO is full and any data written to it will be ignored.
StatusRxFifoEmpty	When set the receive FIFO is empty and any data read from it will be undefined.
StatusIdle	When set the SPI block is idle and can accept a new start command.

Definition at line 116 of file platform-spi.hh.

◆ anonymous enum

anonymous enum : uint32_t

Configuration Register Fields.

Enumerator

ConfigurationHalfClockPeriodMask

The length of a half period (i.e.

positive edge to negative edge) of the SPI clock, measured in system clock cycles reduced by 1. For example, at a 50 MHz system clock, a value of 0 gives a 25 MHz SPI clock, a value of 1 gives a 12.5 MHz SPI clock, a value of 2 gives a 8.33 MHz SPI clock and so on.

Definition at line 54 of file platform-spi.hh.

◆ Interrupt

enum SonataSpi::Interrupt : uint32_t

Sonata SPI Interrupts.

Enumerator
InterruptComplete	Raised when a SPI operation completes and the block has become idle.
InterruptTransmitEmpty	Asserted whilst the transmit FIFO is empty.
InterruptReceiveFull	Asserted whilst the receive FIFO is full.

Definition at line 10 of file platform-spi.hh.

Member Function Documentation

◆ blocking_read()

void SonataSpi::blocking_read	(	uint8_t	data[],
		uint16_t	len ) volatile

inline

Definition at line 219 of file platform-spi.hh.

◆ blocking_write()

void SonataSpi::blocking_write	(	const uint8_t	data[],
		uint16_t	len ) volatile

inline

Sends len bytes from the given data buffer, where len is at most 0x7ff.

Definition at line 185 of file platform-spi.hh.

References control, ControlTransmitEnable, start, StartByteCountMask, status, StatusTxFifoLevel, transmitFifo, and wait_idle().

◆ init()

void SonataSpi::init	(	const bool	ClockPolarity,
		const bool	ClockPhase,
		const bool	MsbFirst,
		const uint16_t	HalfClockPeriod ) volatile

inline

Initialises the SPI block.

Parameters

ClockPolarity	When false, the clock is low when idle and the leading edge is positive. When true, the opposite behaviour is set.
ClockPhase	When false, data is sampled on the leading edge and changes on the trailing edge. When true, the opposite behaviour is set.
MsbFirst	When true, the first bit of each byte sent is the most significant bit, as oppose to the least significant bit.
HalfClockPeriod	The length of a half period of the SPI clock, measured in system clock cycles reduced by 1.

Definition at line 163 of file platform-spi.hh.

References configuration, and ConfigurationHalfClockPeriodMask.

◆ wait_idle()

void SonataSpi::wait_idle ( ) volatile

inline

Waits for the SPI device to become idle.

Definition at line 175 of file platform-spi.hh.

References status, and StatusIdle.

Referenced by blocking_write().

Member Data Documentation

◆ configuration

uint32_t SonataSpi::configuration

Configuration register.

Controls how the SPI block transmits and receives data. This register can be modified only whilst the SPI block is idle.

Definition at line 29 of file platform-spi.hh.

Referenced by init().

◆ control

uint32_t SonataSpi::control

Controls the operation of the SPI block.

This register can be modified only whilst the SPI block is idle.

Definition at line 34 of file platform-spi.hh.

Referenced by blocking_write().

◆ DebugSonataSpi

bool SonataSpi::DebugSonataSpi = false

staticconstexpr

Flag set when we're debugging this driver.

Definition at line 144 of file platform-spi.hh.

◆ interruptEnable

uint32_t SonataSpi::interruptEnable

Definition at line 22 of file platform-spi.hh.

◆ interruptState

uint32_t SonataSpi::interruptState

The Sonata SPI block doesn't currently have support for interrupts.

The following registers are reserved for future use.

Definition at line 21 of file platform-spi.hh.

◆ interruptTest

uint32_t SonataSpi::interruptTest

Definition at line 23 of file platform-spi.hh.

◆ receiveFifo

uint32_t SonataSpi::receiveFifo

Data from the receive FIFO.

When read the data is popped from the FIFO. If the FIFO is empty data read is undefined.

Definition at line 46 of file platform-spi.hh.

◆ start

uint32_t SonataSpi::start

Writes to this begin an SPI operation.

Writes are ignored when the SPI block is active.

Definition at line 41 of file platform-spi.hh.

Referenced by blocking_write().

◆ status

uint32_t SonataSpi::status

Status information about the SPI block.

Definition at line 36 of file platform-spi.hh.

Referenced by blocking_write(), and wait_idle().

◆ transmitFifo

uint32_t SonataSpi::transmitFifo

Bytes written here are pushed to the transmit FIFO.

If the FIFO is full writes are ignored.

Definition at line 51 of file platform-spi.hh.

Referenced by blocking_write().

The documentation for this struct was generated from the following files:

sdk/include/platform/sunburst/v0.2/platform-spi.hh
sdk/include/platform/sunburst/platform-spi.hh

Public Types

Public Member Functions

Public Attributes

Static Public Attributes

Detailed Description

Member Typedef Documentation

◆ Debug

Member Enumeration Documentation

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ Interrupt

Member Function Documentation

◆ blocking_read()

◆ blocking_write()

◆ init()

◆ wait_idle()

Member Data Documentation

◆ configuration

◆ control

◆ DebugSonataSpi

◆ interruptEnable

◆ interruptState

◆ interruptTest

◆ receiveFifo

◆ start

◆ status

◆ transmitFifo