CHERIoT RTOS
A compartmentalised RTOS for CHERIoT hardware
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riscv.h
1// Copyright Microsoft and CHERIoT Contributors.
2// SPDX-License-Identifier: MIT
3
4#ifndef _PRIV_RISCV_H_
5#define _PRIV_RISCV_H_
6
7#include <stddef.h>
8#include <utils.hh>
9
10namespace priv
11{
12#define CSR_ZIMM(val) (__builtin_constant_p(val) && ((unsigned long)(val) < 32))
13
14#define csr_swap(csr, val) \
15 ({ \
16 if (CSR_ZIMM(val)) \
17 __asm __volatile("csrrwi %0, " #csr ", %1" \
18 : "=r"(val) \
19 : "i"(val)); \
20 else \
21 __asm __volatile("csrrw %0, " #csr ", %1" : "=r"(val) : "r"(val)); \
22 val; \
23 })
24
25#define csr_write(csr, val) \
26 ({ \
27 if (CSR_ZIMM(val)) \
28 __asm __volatile("csrwi " #csr ", %0" ::"i"(val)); \
29 else \
30 __asm __volatile("csrw " #csr ", %0" ::"r"(val)); \
31 })
32
33#define csr_set(csr, val) \
34 ({ \
35 if (CSR_ZIMM(val)) \
36 __asm __volatile("csrsi " #csr ", %0" ::"i"(val)); \
37 else \
38 __asm __volatile("csrs " #csr ", %0" ::"r"(val)); \
39 })
40
41#define csr_clear(csr, val) \
42 ({ \
43 if (CSR_ZIMM(val)) \
44 __asm __volatile("csrci " #csr ", %0" ::"i"(val)); \
45 else \
46 __asm __volatile("csrc " #csr ", %0" ::"r"(val)); \
47 })
48
49#define csr_read(csr) \
50 ({ \
51 unsigned int val; \
52 __asm __volatile("csrr %0, " #csr : "=r"(val)); \
53 val; \
54 })
55
56#define wfi() __asm volatile("wfi")
57
58 constexpr size_t MCAUSE_INTR = (1u << 31);
59 constexpr size_t MCAUSE_CODE_MASK = (~MCAUSE_INTR);
60 constexpr size_t MCAUSE_MTIME = 7;
61 constexpr size_t MCAUSE_MEXTERN = 11;
62
63 constexpr size_t MCAUSE_INST_MISALIGNED = 0;
64 constexpr size_t MCAUSE_INST_ACCESS_FAULT = 1;
65 constexpr size_t MCAUSE_ILLEGAL_INSTRUCTION = 2;
66 constexpr size_t MCAUSE_BREAKPOINT = 3;
67 constexpr size_t MCAUSE_LOAD_MISALIGNED = 4;
68 constexpr size_t MCAUSE_LOAD_ACCESS_FAULT = 5;
69 constexpr size_t MCAUSE_STORE_MISALIGNED = 6;
70 constexpr size_t MCAUSE_STORE_ACCESS_FAULT = 7;
71 constexpr size_t MCAUSE_ECALL_USER = 8;
72 constexpr size_t MCAUSE_ECALL_SUPERVISOR = 9;
73 constexpr size_t MCAUSE_ECALL_MACHINE = 11;
74 constexpr size_t MCAUSE_INST_PAGE_FAULT = 12;
75 constexpr size_t MCAUSE_LOAD_PAGE_FAULT = 13;
76 constexpr size_t MCAUSE_STORE_PAGE_FAULT = 15;
77 constexpr size_t MCAUSE_THREAD_EXIT = 24;
78 constexpr size_t MCAUSE_THREAD_INTERRUPT = 25;
79 constexpr size_t MCAUSE_CHERI = 28;
80
81 constexpr size_t MSTATUS_UIE = (1 << 0);
82 constexpr size_t MSTATUS_SIE = (1 << 1);
83 constexpr size_t MSTATUS_HIE = (1 << 2);
84 constexpr size_t MSTATUS_MIE = (1 << 3);
85 constexpr size_t MSTATUS_AIE =
86 (MSTATUS_UIE | MSTATUS_SIE | MSTATUS_HIE | MSTATUS_MIE);
87 constexpr size_t MSTATUS_UPIE = (1 << 4);
88 constexpr size_t MSTATUS_SPIE = (1 << 5);
89 constexpr size_t MSTATUS_SPIE_SHIFT = 5;
90 constexpr size_t MSTATUS_HPIE = (1 << 6);
91 constexpr size_t MSTATUS_MPIE = (1 << 7);
92 constexpr size_t MSTATUS_MPIE_SHIFT = 7;
93 constexpr size_t MSTATUS_SPP = (1 << 8);
94 constexpr size_t MSTATUS_SPP_SHIFT = 8;
95 constexpr size_t MSTATUS_HPP_MASK = 0x3;
96 constexpr size_t MSTATUS_HPP_SHIFT = 9;
97 constexpr size_t MSTATUS_MPP_MASK = 0x3;
98 constexpr size_t MSTATUS_MPP_SHIFT = 11;
99 constexpr size_t MSTATUS_FS_MASK = 0x3;
100 constexpr size_t MSTATUS_FS_SHIFT = 13;
101 constexpr size_t MSTATUS_XS_MASK = 0x3;
102 constexpr size_t MSTATUS_XS_SHIFT = 15;
103 constexpr size_t MSTATUS_MPRV = (1 << 17);
104 constexpr size_t MSTATUS_PUM = (1 << 18);
105 constexpr size_t MSTATUS_VM_MASK = 0x1f;
106 constexpr size_t MSTATUS_VM_SHIFT = 24;
107 constexpr size_t MSTATUS_VM_MBARE = 0;
108 constexpr size_t MSTATUS_VM_MBB = 1;
109 constexpr size_t MSTATUS_VM_MBBID = 2;
110 constexpr size_t MSTATUS_VM_SV32 = 8;
111 constexpr size_t MSTATUS_VM_SV39 = 9;
112 constexpr size_t MSTATUS_VM_SV48 = 10;
113 constexpr size_t MSTATUS_VM_SV57 = 11;
114 constexpr size_t MSTATUS_VM_SV64 = 12;
115 constexpr size_t MSTATUS_SD = (1 << 31);
116
117 constexpr size_t MSTATUS_PRV_U = 0;
118 constexpr size_t MSTATUS_PRV_S = 1;
119 constexpr size_t MSTATUS_PRV_H = 2;
120 constexpr size_t MSTATUS_PRV_M = 3;
121
122 constexpr size_t MIE_USIE = (1 << 0);
123 constexpr size_t MIE_SSIE = (1 << 1);
124 constexpr size_t MIE_HSIE = (1 << 2);
125 constexpr size_t MIE_MSIE = (1 << 3);
126 constexpr size_t MIE_UTIE = (1 << 4);
127 constexpr size_t MIE_STIE = (1 << 5);
128 constexpr size_t MIE_HTIE = (1 << 6);
129 constexpr size_t MIE_MTIE = (1 << 7);
130 constexpr size_t MIE_SEIE = (1 << 9);
131 constexpr size_t MIE_HEIE = (1 << 10);
132 constexpr size_t MIE_MEIE = (1 << 11);
133
134 constexpr size_t MIP_USIP = (1 << 0);
135 constexpr size_t MIP_SSIP = (1 << 1);
136 constexpr size_t MIP_HSIP = (1 << 2);
137 constexpr size_t MIP_MSIP = (1 << 3);
138 constexpr size_t MIP_UTIP = (1 << 4);
139 constexpr size_t MIP_STIP = (1 << 5);
140 constexpr size_t MIP_HTIP = (1 << 6);
141 constexpr size_t MIP_MTIP = (1 << 7);
142 constexpr size_t MIP_SEIP = (1 << 9);
143 constexpr size_t MIE_HEIP = (1 << 10);
144 constexpr size_t MIP_MEIP = (1 << 11);
145
146 static inline size_t intr_disable(void)
147 {
148 size_t ret;
149
150 __asm volatile("csrrci %0, mstatus, %1"
151 : "=&r"(ret)
152 : "i"(MSTATUS_AIE));
153
154 return (ret & (MSTATUS_AIE));
155 }
156
157 static inline void mie_enable()
158 {
159 csr_set(mie, 0x880);
160 }
161
162 static inline void intr_restore(size_t s)
163 {
164 __asm volatile("csrs mstatus, %0" ::"r"(s));
165 }
166
167 static inline void intr_enable()
168 {
169 csr_set(mstatus, 0x08);
170 }
171
172} // namespace priv
173
174#endif // _PRIV_RISCV_H_
utils.hh
Miscellaneous utility functions and classes.
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