A simple driver for Sonata's XADC (Xilinx Analogue to Digital Converter). More...

#include <platform-adc.hh>

Inheritance diagram for SonataAnalogueDigitalConverter:

Collaboration diagram for SonataAnalogueDigitalConverter:

Public Types
enum class	MeasurementRegister : uint8_t { ArduinoA0 = static_cast<uint8_t>(RegisterOffset::VoltageAuxiliary4) , ArduinoA1 = static_cast<uint8_t>(RegisterOffset::VoltageAuxiliary12) , ArduinoA2 = static_cast<uint8_t>(RegisterOffset::VoltageAuxiliary5) , ArduinoA3 = static_cast<uint8_t>(RegisterOffset::VoltageAuxiliary13) , ArduinoA4 = static_cast<uint8_t>(RegisterOffset::VoltageAuxiliary6) , ArduinoA5 = static_cast<uint8_t>(RegisterOffset::VoltageAuxiliary14) , Temperature = static_cast<uint8_t>(RegisterOffset::Temperature) , VoltageInternalSupply , VoltageAuxiliarySupply , VoltageInternalReferencePositive , VoltageInternalReferenceNegative , VoltageBlockRamSupply }
	Represents the offsets of the Xilinx Analogue-to-Digital Converter's (XADC) Dynamic Reconfiguration Port (DRP) status registers that are used to store values that are measured/sampled by the XADC, forming a mapping that provides a more comprehensible interface. More...
enum class	PowerDownMode : uint8_t { None = 0b00 , ConverterB = 0b10 , BothConverters = 0b11 }
	Possible power down modes that can be set in Config Register 2. More...
typedef uint8_t	ClockDivider
	A clock divider value to be used by the Xilinx Analogue-to-Digital Converter (XADC), which divides its input clock (the system clock) by this divider to determine the clock of the XADC.

Public Member Functions
	SonataAnalogueDigitalConverter (ClockDivider divider, PowerDownMode powerDown)
	Constructor - initialises the MMIO capability for the Analogue-to- Digital converter, and then sets its clock divider and power down mode.
	SonataAnalogueDigitalConverter (PowerDownMode powerDown)
	Constructor, without any manual setting of the clock divider.
void	set_clock_divider (ClockDivider divider)
	Sets the clock divider for the Sonata Analogue-to-Digital Converter (ADC), which is used to divide the system clock to create the ADC clock.
void	set_power_down (PowerDownMode powerdown)
	Sets the power down configuration for the Sonata Analogue-to-Digital Converter (ADC).
int16_t	read_last_measurement (MeasurementRegister reg) const
	Reads the most recent output of the analogue-to-digital converter's measurements from a specified status register, corresponding to measurement of some channel.

Static Public Attributes
static constexpr size_t	MaxSamples = 1 * 1000 * 1000
	The Xilinx Analogue-to-Digtal Converter can sample at a maximum rate of 1 Megasample per second.
static constexpr size_t	RegisterSize = 16
static constexpr size_t	MeasurementBitWidth = 12
static constexpr size_t	MinClockFrequencyHz = 1 * 1000 * 1000
	The minimum permissible Analogue-to-Digital Clock speed is 1 MHz, and the maximum is 26 MHz, as per the data sheet.
static constexpr size_t	MaxClockFrequencyHz = 26 * 1000 * 1000

Detailed Description

A simple driver for Sonata's XADC (Xilinx Analogue to Digital Converter).

Documentation source can be found at: https://github.com/lowRISC/sonata-system/blob/97a525c48f7bf051b999d0178dba04859819bc5e/doc/ip/adc.md

Rendered documentation is served from: https://lowrisc.github.io/sonata-system/doc/ip/adc.html

Definition at line 15 of file platform-adc.hh.

Member Typedef Documentation

◆ ClockDivider

typedef uint8_t SonataAnalogueDigitalConverter::ClockDivider

A clock divider value to be used by the Xilinx Analogue-to-Digital Converter (XADC), which divides its input clock (the system clock) by this divider to determine the clock of the XADC.

This clock must fall between specified maximum and minimum frequency, and the divider must be an 8-bit integer, greater than 2.

Definition at line 256 of file platform-adc.hh.

Member Enumeration Documentation

◆ MeasurementRegister

enum class SonataAnalogueDigitalConverter::MeasurementRegister : uint8_t

strong

Represents the offsets of the Xilinx Analogue-to-Digital Converter's (XADC) Dynamic Reconfiguration Port (DRP) status registers that are used to store values that are measured/sampled by the XADC, forming a mapping that provides a more comprehensible interface.

https://lowrisc.github.io/sonata-system/doc/ip/adc.html

Definition at line 193 of file platform-adc.hh.

◆ PowerDownMode

enum class SonataAnalogueDigitalConverter::PowerDownMode : uint8_t

strong

Possible power down modes that can be set in Config Register 2.

https://docs.amd.com/r/en-US/ug480_7Series_XADC/Control-Registers?section=XREF_93518_Power_Down

Definition at line 219 of file platform-adc.hh.

Constructor & Destructor Documentation

◆ SonataAnalogueDigitalConverter() [1/2]

SonataAnalogueDigitalConverter::SonataAnalogueDigitalConverter	(	ClockDivider	divider,
		PowerDownMode	powerDown )

inline

Constructor - initialises the MMIO capability for the Analogue-to- Digital converter, and then sets its clock divider and power down mode.

Takes the clock divider and power down modes to initialise. The clock divider should divide the system clock to create a signal between 1 and 26 MHz, and should be at least 2.

Definition at line 267 of file platform-adc.hh.

References set_clock_divider(), and set_power_down().

◆ SonataAnalogueDigitalConverter() [2/2]

SonataAnalogueDigitalConverter::SonataAnalogueDigitalConverter ( PowerDownMode powerDown )

inline

Constructor, without any manual setting of the clock divider.

Initialises the MMIO capability for the Analogue-to-Digtal converter, and then sets its power down mode.

Takes the power down mode to initialise.

Definition at line 284 of file platform-adc.hh.

References set_power_down().

Member Function Documentation

◆ read_last_measurement()

int16_t SonataAnalogueDigitalConverter::read_last_measurement ( MeasurementRegister reg ) const

inlinenodiscard

Reads the most recent output of the analogue-to-digital converter's measurements from a specified status register, corresponding to measurement of some channel.

This currently assumes unipolar operation, which means all values are positive.

The status register to read the last measurement of is given as the single argument.

The output values can be translated to the relevant units being measured by using the transfer functions defined in documentation: https://docs.amd.com/r/en-US/ug480_7Series_XADC/ADC-Transfer-Functions

Definition at line 340 of file platform-adc.hh.

◆ set_clock_divider()

void SonataAnalogueDigitalConverter::set_clock_divider ( ClockDivider divider )

inline

Sets the clock divider for the Sonata Analogue-to-Digital Converter (ADC), which is used to divide the system clock to create the ADC clock.

The clock divider to use is provided as the single argument. It must be such that it creates a signal between 1 and 26 MHz, and should be at least 2.

Definition at line 300 of file platform-adc.hh.

References MinClockFrequencyHz.

Referenced by SonataAnalogueDigitalConverter().

◆ set_power_down()

void SonataAnalogueDigitalConverter::set_power_down ( PowerDownMode powerdown )

inline

Sets the power down configuration for the Sonata Analogue-to-Digital Converter (ADC).

Calling this function allows either ADC B or the entire XADC to be permanently powered down.

The power down mode to set is provided as an argument.

Definition at line 320 of file platform-adc.hh.

Referenced by SonataAnalogueDigitalConverter(), and SonataAnalogueDigitalConverter().

Member Data Documentation

◆ MaxClockFrequencyHz

size_t SonataAnalogueDigitalConverter::MaxClockFrequencyHz = 26 * 1000 * 1000

staticconstexpr

Definition at line 247 of file platform-adc.hh.

◆ MaxSamples

size_t SonataAnalogueDigitalConverter::MaxSamples = 1 * 1000 * 1000

staticconstexpr

The Xilinx Analogue-to-Digtal Converter can sample at a maximum rate of 1 Megasample per second.

It uses 16 bit Dynamic Reconfiguration Port (DRP) registers, and stores 12-bit measurements, which are stored most- significant-bit justified.

https://docs.amd.com/r/en-US/ug480_7Series_XADC/XADC-Overview

Definition at line 235 of file platform-adc.hh.

◆ MeasurementBitWidth

size_t SonataAnalogueDigitalConverter::MeasurementBitWidth = 12

staticconstexpr

Definition at line 237 of file platform-adc.hh.

◆ MinClockFrequencyHz

size_t SonataAnalogueDigitalConverter::MinClockFrequencyHz = 1 * 1000 * 1000

staticconstexpr

The minimum permissible Analogue-to-Digital Clock speed is 1 MHz, and the maximum is 26 MHz, as per the data sheet.

See table 65 on page 57: https://docs.amd.com/v/u/en-US/ds181_Artix_7_Data_Sheet

Definition at line 246 of file platform-adc.hh.

Referenced by set_clock_divider().

◆ RegisterSize

size_t SonataAnalogueDigitalConverter::RegisterSize = 16

staticconstexpr

Definition at line 236 of file platform-adc.hh.

The documentation for this class was generated from the following file:

sdk/include/platform/sunburst/platform-adc.hh

Public Types

Public Member Functions

Static Public Attributes

Detailed Description

Member Typedef Documentation

◆ ClockDivider

Member Enumeration Documentation

◆ MeasurementRegister

◆ PowerDownMode

Constructor & Destructor Documentation

◆ SonataAnalogueDigitalConverter() [1/2]

◆ SonataAnalogueDigitalConverter() [2/2]

Member Function Documentation

◆ read_last_measurement()

◆ set_clock_divider()

◆ set_power_down()

Member Data Documentation

◆ MaxClockFrequencyHz

◆ MaxSamples

◆ MeasurementBitWidth

◆ MinClockFrequencyHz

◆ RegisterSize